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Espressif Systems /ESP32 /I2C0 /FIFO_CONF

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Interpret as FIFO_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXFIFO_FULL_THRHD 0TXFIFO_EMPTY_THRHD 0 (NONFIFO_EN)NONFIFO_EN 0 (FIFO_ADDR_CFG_EN)FIFO_ADDR_CFG_EN 0 (RX_FIFO_RST)RX_FIFO_RST 0 (TX_FIFO_RST)TX_FIFO_RST 0NONFIFO_RX_THRES 0NONFIFO_TX_THRES

Fields

RXFIFO_FULL_THRHD
TXFIFO_EMPTY_THRHD

Config txfifo empty threhd value when using apb fifo access
NONFIFO_EN

Set this bit to enble apb nonfifo access.
FIFO_ADDR_CFG_EN

When this bit is set to 1 then the byte after address represent the offset address of I2C Slave’s ram.
RX_FIFO_RST

Set this bit to reset rx fifo when using apb fifo access.
TX_FIFO_RST

Set this bit to reset tx fifo when using apb fifo access.
NONFIFO_RX_THRES

when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.
NONFIFO_TX_THRES

when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data